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TMS320C5515
www.ti.com
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
3.2
Power Considerations
The device provides several means of managing power consumption.
To
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minimize power consumption, the device divides its circuits into nine main isolated supply domains:
LDOI (LDOs and Bandgap Power Supply)
Analog POR, SAR, and PLL (V DDA_ANA and V DDA_PLL )
RTC Core (CV DDRTC ) — Note: CV DDRTC must always be powered by an external power source and
none of the on-chip LDOs can be used to power CV DDRTC .
3.2.1
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Digital Core (CV DD )
USB Core (USB_ V DD1P3 and USB_V DDA1P3 )
USB PHY and USB PLL (USB_V DDOSC , USB_V DDA3P3 , and USB_V DDPLL )
EMIF I/O (DV DDEMIF )
RTC I/O (DV DDRTC )
Rest of the I/O (DV DDIO )
LDO Configuration
The device includes three Low-Dropout Regulators (LDOs) which can be used to regulate the power
supplies of the analog PLL and SAR ADC/Power Management (ANA_LDO), Digital Core (DSP_LDO), and
USB Core (USB_LDO).
These LDOs are controlled by a combination of pin configuration and register settings. For more detailed
information see the following sections.
3.2.1.1
LDO Inputs
The LDOI pins (B12, F13, F14) provide power to the internal Analog LDO, DSP LDO, USB LDO, the
bandgap reference generator, and some I/O input pins, and can range from 1.8 V to 3.6 V. The bandgap
provides accurate voltage and current references to the POR, LDOs, PLL, and SAR; therefore, for proper
device operation, power must always be applied to the LDOI pins even if the LDO outputs are not used.
3.2.1.2
LDO Outputs
The ANA_LDOO pin (A12) is the output of the internal ANA_LDO and can provide regulated 1.3 V power
of up to 4 mA. The ANA_LDOO pin is intended to be connected, on the board, to the V DDA_ANA and
V DDA_PLL pins to provide a regulated 1.3 V to the 10-bit SAR ADC, Power Management Circuits, and
System PLL. V DDA_ANA and V DDA_PLL may be powered by this LDO output, which is recommended, to take
advantage of the device's power management techniques, or by an external power supply. The ANA_LDO
cannot be disabled individually (see Section 3.2.1.3 , LDO Control ).
The DSP_LDOO pin (E10) is the output of the internal DSP_LDO and provides software-selectable
regulated 1.3 V or regulated 1.05 V power of up to 250 mA. The DSP_LDOO pin is intended to be
connected, on the board, to the CV DD pins. In this configuration, the DSP_LDO_EN pin should be tied to
the board V SS , thus enabling the DSP_LDO. Optionally, the CV DD pins may be powered by an external
power supply; in this configuration the DSP_LDO_EN pin should be tied (high) to LDOI, disabling
DSP_LDO. Th e DSP_LDO_EN also affects how reset is generated to the chip (for more details, see the
DSP_LDO_EN pin description in Table 2-19 , Regulators and Power Management Terminal Functions ).
When the DSP_LDO is disabled, its output pin is in a high-impedance state. Note: DSP_LDO_EN is not
intended to be changed dynamically.
The USB_LDOO pin (F12) is the output of the internal USB_LDO and provides regulated 1.3 V, software-
switchable (on/off) power of up to 25 mA. The USB_LDOO pin is intended to be connected, on the board,
to the USB_V DD1P3 and USB_V DDA1P3 pins to provide power to portions of the USB. Optionally, the
USB_V DD1P3 and USB_V DDA1P3 may be powered by an external power supply and the USB_LDO can be
left disabled. When the USB_LDO is disabled, its output pin is in a high-impedance state.
Copyright ? 2010–2013, Texas Instruments Incorporated
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Device Configuration
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